Table of Content

1 Autonomous Driving SoC Market and Configuration Data
1.1 Autonomous Driving SoC Market Size and Market Share
1.1.1 Evolution Path of Autonomous Driving: ADAS ? L2 + Driving-parking Integration ? L3/L4 Full Self-driving (FSD) in All Scenarios
1.1.2 Installation Rate of L1-L4 Autonomous Driving Hardware Systems for Passenger Cars in China
1.1.3 China Autonomous Driving SoC Market Size
1.1.4 Global Autonomous Driving SoC Market Size
1.1.5 Market Shares of Autonomous Driving SoC Vendors in China: Summary for 2022 and Outlook for 2023
1.2 Autonomous Driving SoC Deployment Schemes of OEMs
1.2.1 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (1)
1.2.2 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (2)
1.2.3 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (3)
1.2.4 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (4)
1.2.5 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (5)
1.2.6 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (6)
1.2.7 Autonomous Driving SoC Solution Portfolios and System Solution Configurations of OEMs (Including Ongoing Research Projects) (7)
1.3 Application and Configuration Strategy of Autonomous Driving SoC in Driving-parking Integration
1.3.1 Classification of Driving-parking Integration Modes
1.3.2 Configuration Schemes of Some Mainstream Driving-parking Integrated Products Suppliers
1.3.3 "Cost-effective" and "High-performance" Driving-parking Integrated Product and Solution Portfolios of Horizon Robotics
1.3.4 Technical Features Required for Single-SoC Driving-parking Integration
1.3.5 Production and Configuration Schemes of Cost-effective Driving-parking Integrated Chips: Equipped with 1, 2 or 3 SoCs (1)
1.3.6 Production and Configuration Schemes of Cost-effective Driving-parking Integrated Chips: Equipped with 1, 2 or 3 SoCs (2)
1.3.7 Production and Configuration Schemes of Cost-effective Driving-parking Integrated Chips: Equipped with 1, 2 or 3 SoCs (3)
1.3.8 Production and Configuration Schemes of High Performance Driving-parking Integrated Chips: Equipped with 1, 2, 4, 5 or 6 SoCs (1)
1.3.9 Production and Configuration Schemes of High Performance Driving-parking Integrated Chips: Equipped with 1, 2, 4, 5 or 6 SoCs (2)
1.3.10 Typical Driving-parking Integrated Solutions of OEMs: Li Auto AD Pro and AD Max
1.3.11 Typical Driving-parking Integrated Solutions of OEM: Typical Cooperation Cases - Horizon Robotics and Roewe, Li Auto and Geely
1.4 Application Trends of Autonomous Driving SoC in Cockpit-driving Integration
1.4.1 Evolution of Automotive E/E Architecture: from Distributed to Centralized
1.4.2 Evolution of Automotive E/E Architecture: Cockpit-driving Integrated Central Computing Platform Is the Ultimate Form of Automotive AI Computing Architecture
1.4.3 Evolution of Automotive E/E Architecture: Cockpit-driving Integrated E/E Architecture Planning of OEMs
1.4.4 Evolution of Automotive E/E Architecture: Three Cockpit-driving Integration Modes
1.4.5 Challenge 1 in One-box Cockpit-driving Integration: Chip (1)
1.4.6 Challenge 1 in One-box Cockpit-driving Integration: Chip (2)
1.4.7 Challenge 1 in One-box Cockpit-driving Integration: Chip (3)
1.4.8 Challenge 1 in One-box Cockpit-driving Integration: Chip (4)
1.4.9 Challenge 1 in One-box Cockpit-driving Integration: Chip (5)
1.4.10 Challenge 1 in One-box Cockpit-driving Integration: Chip (6)
1.4.11 Challenge 2 in One-box Cockpit-driving Integration: Operating System
1.4.12 Challenge 3 in One-box Cockpit-driving Integration: Hypervisor
1.4.13 Layout Schemes of Cockpit-driving Integrated/Central Computing Platforms
1.4.14 Current Mainstream Cockpit-driving Integrated Solutions of Tier 1 Suppliers
1.4.15 Cockpit-driving Integrated Solution Cases: Jidu JET "All-domain Fusion" Cockpit-driving Integrated Solution
1.4.16 Cockpit-driving Integrated Solution Cases: ECARX Super Brain (Cockpit-driving Integrated Central Computing Platform)
1.4.17 Cockpit-driving Integrated Solution Cases: Evolution Route of Bosch Cockpit-driving Integration (1)
1.4.18 Cockpit-driving Integrated Solution Cases: Evolution Route of Bosch Cockpit-driving Integration (2)
1.4.19 Cockpit-driving Integrated Solution Cases: Desay SV’s Cross-domain Integrated Computing Platform - Aurora (1)
1.4.20 Cockpit-driving Integrated Solution Cases: Desay SV’s Cross-domain Integrated Computing Platform - Aurora (2)
1.4.21 Cockpit-driving Integrated Solution Cases: Desay SV’s Cross-domain Integrated Computing Platform - Aurora (3)
1.4.22 Cockpit-driving Integrated Solution Cases: Desay SV’s Cross-domain Integrated Computing Platform - Aurora (4)


2 Autonomous Driving SoC Selection and Cost
2.1 Comparison of Characteristics between Autonomous Driving SoC Vendors and Their "Turnkey" Solutions
2.1.1 It Needs to Balance Performance, Power Consumption and Cost When Choosing A Right Autonomous Driving SoC
2.1.2 Key Benefits and Features of China-made High-compute Chips
2.1.3 "Turnkey" Solutions of Autonomous Driving SoC Vendors (1)
2.1.4 "Turnkey" Solutions of Autonomous Driving SoC Vendors (2)
2.1.5 The Original Tier 2 Automotive Chip Vendors Have Transformed into Core Suppliers
2.2 Autonomous Driving SoC Selection
2.2.1 Global Autonomous Driving SoC Selection
2.2.2 China Autonomous Driving SoC Selection
2.3 Cost of Autonomous Driving SoC
2.3.1 Cost of Main Autonomous Driving SoC Vendors (1)
2.3.2 Cost of Main Autonomous Driving SoC Vendors (2)
2.3.3 Factors Affecting the Cost of Autonomous Driving SoCs
2.3.4 Single-chip Driving-parking Integrated Solutions for Autonomous Driving Help Automakers Further Reduce Costs


3 Development Trends of Autonomous Driving SoC
3.1 Is It Feasible for OEMs to Independently Make Chips (Autonomous Driving SoC)
3.1.1 Automakers and Autonomous Driving Companies Are Very Willing to Make Chips (Autonomous Driving SoC)
3.1.2 Horizon Robotics Proposes An Open BPU IP Licensing Model and Deepens Cooperation with OEMs to Develop Chips
3.1.3 Key Technologies Required for High-performance Automotive Chip Architecture
3.1.4 It Takes A Long Time to Spawn Autonomous Driving SoCs
3.1.5 Automotive Supply Chain Standard System Specifications That Automotive Chips Need To Meet
3.1.6 Design Method for Autonomous Driving SoC: Purchasing or Self-developing IPs + Building Blocks, with Capital Being the Basic Threshold
3.1.7 Autonomous Driving SoC Network-on-Chip (NOC) IP
3.1.8 Autonomous Driving SoC CPU IP: ARM Cortex-A78AE/ARM Neoverse
3.1.9 Autonomous Driving SoC CPU IP: RISC-V
3.1.10 Autonomous Driving SoC GPU IP
3.1.11 Autonomous Driving SoC NPU IP: AI Accelerator Supplier
3.1.12 Autonomous Driving SoC ISP IP: (1) The Value and Significance of ISP to Autonomous Driving
3.1.13 Autonomous Driving SoC ISP IP: (2) ISP Architecture and Functions of Major Vendors
3.1.14 Autonomous Driving SoC ISP IP: (3)
3.1.15 Summary: Feasible Strategic Options for Automakers to Make Chips
3.2 Application of Chiplet in Autonomous Driving SoC
3.2.1 Three Drivers of Chiplet: "Storage Wall", the Achilles’ Heel of AI Computing Power
3.2.2 Three Drivers of Chiplet: Cost and Yield of High-performance Chips
3.2.3 Three Drivers of Chiplet: Flexibility and IP Reusability
3.2.4 Two Core Technical Frameworks of Chiplet (1): Chiplet Communication Protocol
3.2.5 Two Core Technical Frameworks of Chiplet (2): Underlying Packaging Technology That Supports Chiplet
3.2.6 Chiplet Application Cases
3.2.7 Chiplet Supply Chain in China
3.2.8 As the Boundary between PC and Vehicle Is Blurred, Chiplets Will Shift from Server and PC to Vehicle
3.2.9 More Attempts to Package Automotive Chiplets Will Be Made to Meet Automotive Requirements for Reliability and Cost
3.2.10 Chiplets Will Power Autonomous Driving SoC to Enable Super Heterogeneous Integrated Computing Platforms
3.3 Application of Computing In Memory (CIM) in Autonomous Driving SoC
3.3.1 Significance of Computing In Memory (CIM) to Autonomous Driving
3.3.2 Concept Map of Computing In Memory (CIM) Technology: CIM Breaks the Bottleneck of Von Neumann Architecture
3.3.3 Generalized Computing In Memory (CIM) Solutions: Processing Near Memory, Processing In Memory, and Computing In Memory
3.3.4 Processing In Memory (PIM) Commercialization Cases: Samsung Aquabolt-XL HBM2-PIM
3.3.5 Processing In Memory (PIM) Commercialization Cases: Intel Neuromorphic Computing Chip - Loihi
3.3.6 Processing In Memory (PIM) Commercialization Cases: AMD MI300 GPU
3.3.7 Real Storage and Computing Integration: Computing In Memory (CIM)
3.3.8 Computing In Memory (CIM) Faces the Main Challenge of Choosing Storage Medium Technology Route
3.3.9 CIM Chip Companies in China and Their Selection of Technology Route


4 Global Autonomous Driving Chip Vendors
4.1 NVIDIA
4.1.1 Automotive Business in 2022
4.1.2 Autonomous Driving Chip Strategy
4.1.3 Autonomous Driving SoC Portfolio
4.1.4 Thor Central Computer
4.1.4.1 Release of Thor (Nvidia Cancels Atlan Chip and Launches Thor to Replace Orin SoC)
4.1.4.2 Thor: FP8 Formats in Cooperation with ARM and Intel
4.1.4.3 Thor: Automotive Centralized Computers
4.1.4.4 Thor Architecture Design
4.1.5 ORIN SoC
4.1.5.1 ORIN SoC Architecture: Frame Diagram
4.1.5.2 ORIN SoC Architecture: Functional Design
4.1.5.3 ORIN SoC Architecture: CPU
4.1.5.4 ORIN SoC Architecture: GPU
4.1.5.5 ORIN SoC Architecture: Deep Learning Accelerator (DLA)
4.1.5.6 ORIN SoC Architecture: Programmable Vision Accelerator (PVA) and (VPI)
4.1.5.7 ORIN SoC Architecture: Interfaces
4.1.5.8 Frame Diagram of Intelligent Driving Domain Controllers with Orin as the Core
4.1.5.9 ORIN Series: ORIN-X/ORIN-N, etc.
4.1.5.10 ORIN Lineup: entry-level ORIN-Nano
4.1.6 Autonomous Driving "Turnkey" Solution: Hyperion
4.1.6.1 Drive Hyperion Technology Roadmap
4.1.6.2 Strategic Cooperation with Foxconn Based on Drive Hyperion Design Architecture
4.1.6.3 Drive Hyperion 9 Will Be Launched in 2024 and Mounted on Vehicles in 2026
4.1.6.4 Drive Hyperion 9 Will Adopt the Latest Hopper GPU Architecture
4.1.6.5 Drive Hyperion 8
4.1.6.6 Drive Hyperion 8.1: Development Platform Architecture for L2+
4.1.6.7 Drive Hyperion 8.1: Development Platform Architecture for L3
4.1.6.8 Drive Hyperion 8.1: Development Platform Architecture for L3/L4
4.1.6.9 Drive Hyperion 8.1: Velodyne LiDAR
4.1.6.10 Drive Hyperion 8.1: Broadcom BCM8957X Ethernet Switch
4.1.6.11 DRIVE AutoPilot (for L2+, based on Xavier)
4.1.7 Autonomous Driving Software and Algorithms
4.1.7.1 Autonomous Driving Full Stack Toolchain
4.1.7.2 Software Solutions
4.1.7.3 Algorithm Library: VPI

4.2 Mobileye
4.2.1 Operating Performance in 2022: Orders and Major Customers
4.2.2 Operating Performance in 2022: Forecast for SuperVision Mass Production
4.2.3 Operating Performance in 2022: Significant Increase in SoC Shipments and ASP
4.2.4 Redefining ODD from the Perspective of Consumers
4.2.5 Defining Eyes-off ODD from the Perspective of Consumers
4.2.6 Roadmap of Consumer-based Redefined ODD Chips, Sensors and Domain Controllers
4.2.7 Product Portfolio: L2-L4 Autonomous Driving Solutions
4.2.8 Product Portfolio: L4 Solutions
4.2.9 Product Portfolio: Domain Controller Design Reference
4.2.10 Main Intelligent Driving Solutions: EyeQ5+SuperVision for L2+
4.2.11 Main Intelligent Driving Solutions: L4 Drive for L3/L4.
4.2.12 Main Intelligent Driving Solutions: L4 Autonomous Driving Solutions Based on Six EyeQ5 Chips
4.2.13 Tools and Software: EyeQ Toolkit and REM Crowdsourced Mapping
4.2.14 Tools and Software: REM Crowdsourced Mapping
4.2.15 Sensors: 4D Imaging Radar, Flash LiDAR, FMCW LiDAR
4.2.16 Sensors: Performance Estimation of 4D Imaging Radar
4.2.17 Sensors: Upcoming Cooperation with Wistron NeWeb Corporation (WNC) in Producing Software-defined Imaging Radar
4.2.18 Sensors: Planned Provision of Autonomous Driving Kit including Chips/Vision/Radar
4.2.19 Autonomous Driving SoC Portfolio
4.2.20 EyeQ Lineup: Typical Technical Parameters
4.2.21 EyeQ Lineup: EyeQ Ultra, EyeQ6L and EyeQ6H
4.2.22 EyeQ Lineup: EyeQ? Ultra? SoC
4.2.23 EyeQ Lineup: System Architecture of EyeQ? Ultra?
4.2.24 EyeQ Lineup: EyeQ? 6L/6H SoC
4.2.25 EyeQ Lineup: Architecture Diagram of EyeQ? 6H SoC
4.2.26 EyeQ Lineup: Architecture Diagram of EyeQ? 6L SoC
4.2.27 EyeQ Lineup: EyeQ6 with Intel Atom
4.2.28 EyeQ Lineup: Frame Diagram of EyeQ5 SoC
4.2.29 EyeQ Lineup: Functional Module Diagram of EyeQ5 SoC
4.2.30 EyeQ Lineup: EyeQ5 SoC Open Platform (allowing third-party code to run)
4.2.31 EyeQ Lineup: EyeQ4 SoC

4.3 Qualcomm
4.3.1 Automotive Business in 2022
4.3.2 Autonomous Driving SoCs: Snapdragon Ride Flex SoC
4.3.3 Autonomous Driving SoCs: Snapdragon Ride SoC (SA8540P+ SA9000P)
4.3.4 Autonomous Driving SoCs: Topological Architecture of Snapdragon Ride SoC
4.3.5 Autonomous Driving SoCs: Snapdragon Ride Development Platform
4.3.6 Autonomous Driving SoCs: Snapdragon Ride Platform and Arriver Software Stack
4.3.7 Autonomous Driving "Turnkey" Solution: Snapdragon Ride? platform
4.3.8 Autonomous Driving Software: Arriver Vision Software Stack
4.3.9 Autonomous Driving Customers

4.4 TI
4.4.1 Operation in 2022
4.4.2 Automotive Business Layout
4.4.3 Autonomous Driving SoC Portfolio
4.4.4 Jacinto 7 Automotive Processor Platform: Overview
4.4.5 Jacinto 7 Automotive Processor Platform: Multifunctional Integration of ADAS-SoC
4.4.6 Jacinto 7 Automotive Processor Platform: Hyperheterogeneous Design
4.4.7 Autonomous Driving SoCs: TDA4x SoC Family
4.4.8 Autonomous Driving SoCs: Applications of TDA4x SoC
4.4.9 Autonomous Driving SoCs: TDA4AH SoC (Pre-release)
4.4.10 Autonomous Driving SoCs: TDA4VM SoC (Mass-produced)
4.4.11 Autonomous Driving SoCs: Application Frame Diagram of TDA4VM SoC
4.4.12 Autonomous Driving SoCs: Core Features of TDA4VM SoC - Multi-stage Processing and Low Power Consumption
4.4.13 Autonomous Driving SoCs: Functional Safety Island of TDA4VM MCU
4.4.14 Autonomous Driving Software Algorithms: Matrix Multiply Accelerator (MMA) for Deep Learning of TDA4VM SoC
4.4.15 Autonomous Driving Software Algorithms: Deep Learning (DL)
4.4.16 Autonomous Driving Software Algorithms: TDA4x SoC Automated Parking Data Flow
4.4.17 Autonomous Driving Software Algorithms: TDA4x SoC Software Stack and Load
4.4.18 Autonomous Driving Software Algorithms: OpenVX, the Key Algorithm of TDA4x SoC
4.4.19 Application Cases of Autonomous Driving SoCs

4.5 Renesas
4.5.1 Automotive Business in 2022
4.5.2 Automotive Chip Capacity and Expansion Plan (1)
4.5.3 Automotive Chip Capacity and Expansion Plan (2)
4.5.4 Automotive Chip Business Strategy (1): Continuous M & A for Expanding Business Scope
4.5.5 Automotive Chip Business Strategy (2): Continuous M & A for Expanding Business Scope
4.5.6 Automotive Chip Business Strategy (3): ADAS and "Electric Drive, Battery and Electric Control? Chips
4.5.7 Automotive Chip Business Strategy (4): ADAS and "Electric Drive, Battery and Electric Control? Chips
4.5.8 Automotive Chip Business Strategy (4): Cross-Domain/Zone Architecture
4.5.9 Autonomous Driving SoC Portfolio (1)
4.5.10 Autonomous Driving SoC Portfolio (2)
4.5.11 Autonomous Driving SoCs: R-Car Series
4.5.12 Autonomous Driving SoCs: R-Car ADAS Chip Roadmap
4.5.13 Autonomous Driving SoCs: R-Car V3U SoC
4.5.14 Autonomous Driving SoCs: Key Features of R-Car V3U SOC
4.5.15 Autonomous Driving SoCs: Internal Framework of R-Car V3U SoC
4.5.16 Autonomous Driving SoCs: Video Processing Pipeline of R-Car V3U SoC
4.5.17 Autonomous Driving SoCs: R-Car V3U SoC Adopts Low-power Imagination GPU
4.5.18 Autonomous Driving SoCs: Modular Design of R-Car V3U SoC
4.5.19 Autonomous Driving SoCs: Global Customer Base of R-Car V3U SoC
4.5.20 Autonomous Driving SoCs: R-Car V3H SoC
4.5.21 Autonomous Driving SoCs: Block Diagram of R-Car V3H SoC
4.5.22 Autonomous Driving SoCs: Performance Parameters of R-Car V3H SoC
4.5.23 Autonomous Driving SoCs: R-Car V3H SoC Features Ultra-low Power
4.5.24 Autonomous Driving SoCs: R-Car V3H SoC Has Outstanding Visual Performance
4.5.25 Autonomous Driving SoCs: R-Car V3H SoC Is Applied to L4 Computing Platforms
4.5.26 Autonomous Driving SoCs: R-Car V3H2 SoC Is an Upgraded Version of R-Car V3H SoC
4.5.27 Autonomous Driving SoCs: Block Diagram of R-Car V3M SoC
4.5.28 Autonomous Driving "Turnkey" Solution: EagleCAM Developer Platform
4.5.29 Autonomous Driving Software: R-Car Software Development Kit (SDK)
4.5.30 Autonomous Driving Software: Cross-platform, Scalable and Reusable R-Car

4.6 Ambarella
4.6.1 Profile
4.6.2 Global Business Layout
4.6.3 Technology and Product Strategies: "Algorithm First"
4.6.4 Technology and Product Strategies: Prioritizing Visual Solutions
4.6.5 Technology and Product Strategies: AI Intelligent Algorithm Accelerator Architecture - CVflow
4.6.6 Technology and Product Strategies: Emphasis on Computational Efficiency
4.6.7 Technology and Product Strategies: Acquisition of Oculii, a radar company
4.6.8 Technology and Product Strategies: Oculii’s Core Technology - Virtual Aperture AI Radar Algorithm
4.6.9 Technology and Product Strategies: Scenario Examples of Oculii’s 4D Imaging Radar
4.6.10 Technology and Product Strategies: Focus on Centralized 4D Imaging Radar Architecture
4.6.11 Technology and Product Strategies: Comparison between Centralized and Edge 4D Imaging Processing Technologies
4.6.12 Autonomous Driving SoCs: Portfolio
4.6.13 Autonomous Driving SoCs: Application Fields
4.6.14 Autonomous Driving SoCs: Product Architecture
4.6.15 Autonomous Driving SoCs: CV3
4.6.16 Autonomous Driving SoCs: A Number of CV3 Series Chips with Different Positioning Solutions Will Be Launched in the Future
4.6.17 Autonomous Driving SoCs: Domain Controller Architecture Based on CV3
4.6.18 Autonomous Driving SoCs: Ambarella Expanded CV3 Family of Automotive AI Domain Controllers with New CV3-AD685 at CES 2023
4.6.19 Autonomous Driving SoCs: Key Features of CV3-AD685
4.6.20 Autonomous Driving SoCs: What Can CV3-AD685 Bring to Customers?
4.6.21 Autonomous Driving SoCs: Tier1 Customers of CV3-AD685
4.6.22 Autonomous Driving SoCs: CV2x Series AI Vision Autonomous Driving Chips
4.6.23 Autonomous Driving SoCs: CV2x Series, CV22AQ
4.6.24 Autonomous Driving SoCs: CV2x Series, CV22FS and CV2FS
4.6.25 Autonomous Driving SoCs: Cooperation Cases of CV2x Series
4.6.26 Automotive Software Partners

4.7 NXP
4.7.1 Operation in 2022
4.7.2 Autonomous Driving SoC Portfolio
4.7.3 S32x Series Chip Lineup
4.7.4 S32 ADAS Chips
4.7.5 S32 ADAS Chip Technology Route
4.7.6 Architecture Features of S32V2/S32V3 ADAS Chips
4.7.7 AI Tool Software Development Kit
4.7.8 BlueBox3.0 Computing Platform

4.8 Xilinx
4.8.1 AMD Acquired the World’s Largest FPGA Maker Xilinx in 2022
4.8.2 AMD’s Operation in 2022
4.8.3 Automotive Business
4.8.4 Application Fields of ADAS/AD Products
4.8.5 FPGA Devices Conform to the Development Trend of ADAS Sensors
4.8.6 Route and Layout of FPGA Devices
4.8.7 Autonomous Driving SoC Portfolio (1)
4.8.8 Autonomous Driving SoC Portfolio (2)
4.8.9 The Next-generation Automotive-grade Versal AI Edge Series (7nm)
4.8.10 SoC+FPGA Series Products
4.8.11 Expandable Product Series
4.8.12 Versal ACAP Series (1)
4.8.13 Versal ACAP Series (2)
4.8.14 Features of Zynq UltraScale+ MPSoC
4.8.15 Autonomous Driving System Based on FPGA+CPU
4.8.16 Unified Software Platform For AI and Machine Learning & Reasoning: Vitis AI 2.0
4.8.17 Unified Software Development Platform: Vitis AI 1.0 Accelerating Xilinx’s Transformation into a Software Supplier
4.8.18 Unified Software Development Platform: Application of Vitis AI 1.0 in Smart Cars
4.8.19 AD System Architecture Solutions
4.8.20 FPGA Empowers Binocular Vision and 4D Radar
4.8.21 FMCW Empowers LiDAR
4.8.22 FPGA Empowers Intelligent Cockpit DMS/ICMS
4.8.23 FPGA Empowers Autonomous Driving Sensor Fusion
4.8.24 FPGA Empowers New Energy Vehicles
4.8.25 FPGA Empowers Security Gateways

4.9 Tesla
4.9.1 System Parameter Evolution of FSD HW1.0-HW4.0
4.9.2 HW4.0 Computing Platform (1)
4.9.3 HW4.0 Computing Platform (2)
4.9.4 HW4.0 Computing Platform (3)
4.9.5 HW4.0 Computing Platform (4)
4.9.6 HW4.0 Computing Platform (5)
4.9.7 HW3.0 SoC: Chip IP
4.9.8 HW3.0 SoC: Chip Internal Structure
4.9.9 HW3.0 SoC: NNA Design Principle, Initial Network, Circular Convolution and Actuation
4.9.10 HW3.0 SoC NPU Design
4.9.11 Automotive Central Computing Platform: Interconnected via PCIe


5 Chinese Autonomous Driving Chip Vendors
5.1 Horizon Robotics
5.1.1 Business Models: Four Cooperation Modes Positioned at Tier2
5.1.2 Business Models: Shelf-style Product Portfolio Positioned at Tier2
5.1.3 Business Models: BPU IP Authorization Mode
5.1.4 Business Models: Establishment of a Joint Venture with Volkswagen CARIAD
5.1.5 Product Portfolio (1)
5.1.6 Product Portfolio (2)
5.1.7 Journey Series AI Chips: Continuous Evolution from Gaussian Architecture, Bernoulli Architecture, Bayesian Architecture to Nash Architecture
5.1.8 Journey Series AI Chips: Technology Roadmap
5.1.9 Journey Series AI Chips: Development Concept of J6 (BPU with Nash Architecture)
5.1.10 Journey Series AI Chips: J5 (1) - Bayesian Architecture
5.1.11 Journey Series AI Chips: J5 (2) - System Parameters
5.1.12 Journey Series AI Chips: J5 (3) - Neural Network Model
5.1.13 Journey Series AI Chips: J5 (4) - High-speed NOA
5.1.14 Journey Series AI Chips: J5 (5) - City NOA Based on a Single Chip
5.1.15 Journey Series AI Chips: J5 (6) - Security Management System
5.1.16 Journey Series AI Chips: J5 (7) - Functional Safety Certification
5.1.17 Journey Series AI Chips: J5 (8) - Ecosystem Construction
5.1.18 Journey Series AI Chips: J3 (1)
5.1.19 Journey Series AI Chips: J3 (2)
5.1.20 Journey Series AI Chips: J2 (1)
5.1.21 Journey Series AI Chips: J2 (2)
5.1.22 Journey Series AI Chips: Technical Parameters of J2, J3 and J5
5.1.23 Journey Series AI Chips: The Maximum Computing Performance of FPS Is Continuously Improved through the Compiler
5.1.24 Intelligent Computing Reference Platform: Evolution of Horizon Matrix Series
5.1.25 Intelligent Computing Reference Platform: Parameters of Matrix 5 Series
5.1.26 Intelligent Computing Reference Platform: Matrix 5 Verification and Adaptation Process
5.1.27 Intelligent Computing Reference Platform: Matrix 5 Mass Production Acceleration Software Package
5.1.28 Intelligent Computing Reference Platform: Matrix 5 Cooperation Modes, Hardware IDH Partners
5.1.29 "Turnkey" Solutions: Front View ADAS and L2+ Solutions Based on Journey 3
5.1.30 "Turnkey" Solutions: Horizon Matrix? FSD Solution Based on Journey 5
5.1.31 "Turnkey" Solutions: Horizon Halo? Automotive Intelligent Interactive Solution Based on Journey 3
5.1.32 "Turnkey" Solutions: Horizon Matrix Mono 2.0 - Monocular Front View Solution Based on Journey 2
5.1.33 Driving and Parking Integrated Solutions: Different Chips for Diversified Demand
5.1.34 Driving and Parking Integrated Solutions: A Number of Tier1 Suppliers Have Realized Mass Production and Applications of Driving and Parking Integrated Solutions Based on Journey Chips
5.1.35 Driving and Parking Integrated Solutions: OEM Mass Production Cases
5.1.36 Software and Toolchain: Framework
5.1.37 Software and Toolchain: Together OS - RTOS with Microkernel Architecture (1)
5.1.38 Software and Toolchain: Together OS - RTOS with Microkernel Architecture (2)
5.1.39 Software and Toolchain: TGCW AI Chip Toolchain (1)
5.1.40 Software and Toolchain: TGCW AI Chip Toolchain (2)
5.1.41 Software and Toolchain: TGCW AI Chip Toolchain (3)
5.1.42 Software and Toolchain: ?AIDI" Data Closed-loop Development Platform
5.1.43 Computing Architecture: Migration from "Intelligent Computing 1.0" to "Intelligent Computing 2.0"
5.1.44 Customer System: Pursuit of "More, Faster, Better and More Economical"
5.1.45 Customer System: The Shipments Had Exceeded 2 Million Units by the end of 2022
5.1.46 Customer System: The Latest Cooperation Case with Tier1 Supplierss

5.2 Black Sesame Technologies
5.2.1 Profile
5.2.2 Market Positioning: Tier 2 Supplier
5.2.3 Core Technical Features
5.2.4 AI Chip Portfolio
5.2.5 Wudang Series Chips: C1200 Cross-domain Computing Chip for Smart Cars
5.2.6 Wudang Series Chips: C1200 Supports Single-chip Cross-domain Computing Scenarios, Providing a Cost-Effective Solution
5.2.7 Huashan Series Chips: Technology Roadmap
5.2.8 Huashan Series Chips: Topology Diagram of Development Technology Environment
5.2.9 Huashan Series Chips: Key Technology Layout
5.2.10 Huashan Series Chips: Index Parameters of A1000L/ A1000/ A1000 Pro Chips
5.2.11 Huashan Series Chips: Huashan No.2 A1000 Pro
5.2.12 Huashan Series Chips: Huashan No.2 A1000 - System Block Diagram
5.2.13 Huashan Series Chips: Huashan No.2 A1000 - Key Technical Parameters
5.2.14 Huashan Series Chips: Huashan No.2 A1000/A1000L - Key Performance Parameters
5.2.15 Huashan Series Chips: Multiple Automotive-grade Certifications
5.2.16 Autonomous Driving Software and Hardware Reference Solutions: Drive-BEST
5.2.17 Autonomous Driving Software and Hardware Reference Solutions: FAD Autonomous Driving Computing Platform
5.2.18 AI Algorithm Development Toolchain: "Shanhai Artificial Intelligence Development Platform”
5.2.19 "Turnkey" Solutions: Drive Sensing - High-level Single-SoC Driving and Parking Integrated Solution
5.2.20 "Turnkey" Solutions: End-to-end Full Stack Perception Solution
5.2.21 CVIS Layout: FAD Edge Roadside Perception Computing Platform
5.2.22 CVIS Layout: Cooperation with Baidu PaddlePaddle in CVIS Industrial Ecology
5.2.23 Cooperation and Mass Production Projects
5.2.24 5.2.29 Ecosystem

5.3 SemiDrive
5.3.1 Profile
5.3.2 Processor Lineup
5.3.3 Processor Layout: Future Central Computing Architecture
5.3.4 Central Computing Architecture: SCCA 1.0
5.3.5 Autonomous Driving Chips: Product Roadmap
5.3.6 Autonomous Driving Chips: Product Portfolio
5.3.7 Autonomous Driving Chips: Comparison between Index Parameters of V9L/V9F/V9T Chips
5.3.8 Autonomous Driving Chips: Features of V9T SoC
5.3.9 Autonomous Driving Chips: Architectural Diagram of V9T SoC
5.3.10 Autonomous Driving Chips: Block Diagram of V9T SoC
5.3.11 Autonomous Driving Platform: UniDrive
5.3.12 Ecological Partners

5.4 Huawei
5.4.1 Autonomous Driving SoC Portfolio
5.4.2 Autonomous Driving SoCs: Ascend 910/310 Main Control Chip
5.4.3 Autonomous Driving SoCs: Ascend 910/310 with Huawei’s Self-developed DaVinci Architecture
5.4.4 Autonomous Driving SoCs: Performance Parameters of Ascend 310
5.4.5 Autonomous Driving SoCs: Performance Parameters of Ascend 910
5.4.6 Autonomous Driving SoCs: Ascend Chip Technology Route Planning
5.4.7 Autonomous Driving SoCs: Application in MDC Computing Platform

5.5 HOUMO.AI
5.5.1 Focus on High Computing Power AI Chips Integrating Storage and Computing
5.5.2 Technical Background of "Integration of Storage and Computing": High Computing Power + Low Power Consumption
5.5.3 Technical Background of "Integration of Storage and Computing": Physical Computing Power of More Than 60 TOPS under Natural Air Cooling
5.5.4 Architecture Design Concept of AI Chips Integrating Storage and Computing
5.5.5 Automotive High Computing Power Chips Integrating Storage and Computing
5.5.6 Roadmap of Automotive High Computing Power Chips
5.5.7 AI Development To