Table of Content


1 INTRODUCTION
1.1 Study Deliverables
1.2 Study Assumptions
1.3 Scope of the Study


2 RESEARCH METHODOLOGY


3 EXECUTIVE SUMMARY


4 MARKET DYNAMICS
4.1 Market Overview
4.2 Introduction to Market Drivers and Restraints
4.3 Market Drivers
4.3.1 High Packaging Density Leading to Miniaturization
4.3.2 Advancements in Electronics Packaging is Causing the Market to Expand
4.4 Market Restraints
4.4.1 High Cost Associated With Flip Chip Technology
4.5 Value Chain Analysis
4.6 Industry Attractiveness - Porter’s Five Force Analysis
4.6.1 Threat of New Entrants
4.6.2 Bargaining Power of Buyers/Consumers
4.6.3 Bargaining Power of Suppliers
4.6.4 Threat of Substitute Products
4.6.5 Intensity of Competitive Rivalry


5 MARKET SEGMENTATION
5.1 By Product
5.1.1 Memory
5.1.2 Light-Emitting Diode
5.1.3 CMOS Image Sensor
5.1.4 SoC
5.1.5 GPU
5.1.6 CPU
5.2 By Wafer Bumping Process
5.2.1 Copper Pillar
5.2.2 Tin-Lead Eutectic Solder
5.2.3 Lead Free Solder
5.2.4 Gold Stud Bumping
5.3 By Packaging Technology
5.3.1 2D IC
5.3.2 2.5D IC
5.3.3 3D IC
5.4 By Application
5.4.1 Military & Defense
5.4.2 Medical & Healthcare
5.4.3 Industrial Sector
5.4.4 Automotive
5.4.5 Consumer Electronics
5.4.6 Telecommunication
5.4.7 Other Applications
5.5 Geography
5.5.1 North America
5.5.2 Europe
5.5.3 Asia-Pacific
5.5.4 Latin America
5.5.5 Middle East & Africa


6 COMPETITIVE LANDSCAPE
6.1 Company Profiles
6.1.1 Amkor Technology Inc.
6.1.2 IBM Corporation
6.1.3 Intel Corporation
6.1.4 Taiwan Semiconductor Manufacturing Company Limited
6.1.5 Samsung Electronics Co. Ltd.
6.1.6 Texas Instruments Inc.
6.1.7 GlobalFoundries U.S. Inc.
6.1.8 STATS ChipPAC Ltd
6.1.9 Powertech Technology (Singapore) Pte. Ltd.


7 INVESTMENT ANALYSIS


8 MARKET OPPORTUNITIES AND FUTURE TRENDS