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NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors’ VT). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.
Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.
To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors.
This report provides detailed analysis of worldwide markets for NAND Flash from 2011-2015 and provides extensive market forecasts 2016-2021 by region/country and subsectors. It covers the key technological and market trends in the NAND Flash market and further lays out an analysis of the factors influencing the supply/demand for NAND Flash, and the opportunities/challenges faced by industry participants. It also acts as an essential tool to companies active across the value chain and to the new entrants by enabling them to capitalize the opportunities and develop business strategies.
GCC’s report, Global NAND Flash Market Outlook 2016-2021, has been prepared based on the synthesis, analysis, and interpretation of information about the global NAND Flash market collected from specialized sources. The report covers key technological developments in the recent times and profiles leading players in the market and analyzes their key strategies. The competitive landscape section of the report provides a clear insight into the market share analysis of key industry players. The major players in the global NAND Flash market are Samsung (South Korea), Toshiba (Japan), Micron (USA), SK Hynix (South Korea), among others.
The report provides separate comprehensive analytics for the North America, Europe, Asia-Pacific, Middle East and Africa and Rest of World. In this sector, global competitive landscape and supply/demand pattern of NAND Flash industry has been provided.